Semiconductor Logic

Semiconductor Logic

I spent a decade working on the design of unique silicon architectures based on iconic principles. The basic challenge is to develop new arrangements for familiar logic gates that compute in unfamiliar ways. Of course the multi-billion dollar silicon chip industry has mastered the design of logic gates, so it is rather surprising that new architectures are even possible. But the blistering pace of development in silicon technologies has left little time for exploration or for experimentation. The inertia is so great that doubling or tripling efficiency, for example, is not seen as an improvement if it involves a major change in the techniques that the industry has established. Retraining thousands of highly skilled engineers to understand and to use substantially different approaches is not a commercial win. The Image shows an early silicon architecture, known as a two-level PLA.


Distinction Networks

This work was first published in 1989 in an esoteric journal Future Computing Systems as An Introduction to Boundary Logic with the Losp Deductive Engine. The implementation demonstrated that the evaluation of logic (and thus circuit design) can incorporate significant parallelism. We showed this system at IJCAI’87 running on a 16-node Intel hypercube. Incidentally, with the total domination of the sequential CPU (Central Processing Unit), computer architectures that rely on massive parallelism have all but disappeared.

The Distinction Networks paper shows a design that permits logic nodes to communicate only with neighbors to enact computation; coordination with other non-neighbor nodes is not necessary. The central idea behind strong parallelism is that each logic unit or gate operates independently, without global coordination or synchronization. Asynchronous computing has been on the horizon for over three decades, but it too has all but disappeared.


Circuit Schematics

In an entirely different project, I wrote software that configures silicon functionality to pre-specified desired structural parameters. The CM85a Circuit Schematics paper shows 34 different structural architectures for the same circuit. The presentation is entirely visual. The simple CM85a circuit compares two four-bit numbers to determine if they are equal and if not, to identify the larger and the smaller number. The different schematics show function optimization, circuit library design constraints, hierarchical abstraction, and several exotic architectures based on iconic logic.



W. Bricken and E. Gullichsen (1989) An Introduction to Boundary Logic with the Losp Deductive Engine, Future Computing Systems 2(4), 1-77.

W. Bricken (1995) Distinction Networks. in I. Wachsmuth, C.R. Rollinger & W. Brauer (eds.) KI-95: Advances in Artificial Intelligence., Springer, 35-48.